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| encore? v low voltage microcontroller cy7c604xx cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-12395 rev *j revised september 15, 2009 features powerful harvard architecture processor ? m8c processor speeds running up to 24 mhz ? low power at high processing speeds ? interrupt controller ? 1.71v to 3.6v operating voltage ? commercial temperature range: 0c to +70c flexible on-chip memory ? up to 32k flash program storage ? 50,000 erase and write cycles ? flexible protection modes ? up to 2048 bytes sram data storage ? in-system serial programming (issp) complete development tools ? free development tool (psoc designer?) ? full featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k trace memory precision, programmable clocking ? crystal-less oscillator with support for an external crystal or resonator ? internal 5.0% 6, 12, or 24 mhz main oscillator ? internal low speed oscillator at 32 khz for watchdog and sleep.the frequency range is 19 to 50 khz with a 32 khz typical value programmable pin configurations ? up to 36 gpio (depending on package) ? 25 ma sink current on all gpio ? pull up, high z, open drain, cmos drive modes on all gpio ? cmos drive mode (5 ma source current) on ports 0 and 1: ? 20 ma (at 3.0v) total source current ? low dropout voltage regulator for port 1 pins: ? programmable to output 3.0, 2.5, or 1.8v ? selectable, regulated digital i/o on port 1 ? configurable input threshold for port 1 ? hot-swappable capability on port 1 additional system resources ? configurable communication speeds ? i 2 c slave ? selectable to 50 khz, 100 khz, or 400 khz ? implementation requires no clock stretching ? implementation during sleep modes with less than 100 ma ? hardware address detection ? spi master and spi slave ? configurable between 46.9 khz and 12 mhz ? three 16-bit timers ? 10-bit adc used to monitor batt ery voltage or other signals with external components ? watchdog and sleep timers ? integrated supervisory circuit encore v lv block diagram system bus 6/12/24 mhz internal main oscillator cpu core (m8c) srom 8k/16k/32k flash system resources i2c slave/spi master-slave por and lvd system resets port 1 port 0 sleep and watchdog port 3 port 2 prog. ldo sram 2048 bytes interrupt controller encore v core 3 16-bit timers port 4 adc [+] feedback
cy7c604xx document number: 001-12395 rev *j page 2 of 33 functional overview the encore v lv family of devices are designed to replace multiple traditional low voltag e microcontroller system compo- nents with one, low cost single chip programmable component. communication peripherals (i 2 c/spi), a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts. the architecture for this device family, as illustrated in encore v lv block diagram, is comprised of two main areas: the cpu core and the system resources. depending on the encore v lv package, up to 36 general purpose io (gpio) are also included. enhancements over the cypress?s legacy low voltage microcon- trollers include faster cpu at lower voltage operation, lower current consumption, twice t he ram and flash, hot-swapable i/os, i 2 c hardware address recognition, new very low current sleep mode, and new package options. the encore v lv core the encore v lv core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo (internal main oscillator) and ilo (internal low speed oscillator). the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a four-mips, 8-bit harvard architecture microprocessor. system resources provide additional capability, such as a configurable i 2 c slave and spi master-slave communication interface and various system re sets supported by the m8c. 10-bit adc the adc on encore v lv device is an independent block with a state machine interface to cont rol accesses to the block. the adc is housed together with the temperature sensor core and can be connected to this or the analog mux bus. as a default operation, the adc is connec ted to the tem perature sensor diodes to give digital values of the temperature. figure 1. adc system performance block diagram the adc user module contains an integrator block and one comparator with positive and n egative input set by the muxes. the input to the integrator stage comes from the analog global input mux or the temperature sens or with an input voltage range of 0v to 1.3 v, where 1.3v is 72% of full scale. in the adc only configuration (the adc mux selects the analog mux bus, not the default temper ature sensor connection), an external voltage can be connected to the input of the modulator for voltage conversion. the ad c is run for a number of cycles set by the timer, depending upon the resolution of the adc desired by the user. a counter counts the number of trips by the comparator, which is proportional to the input voltage. the temp sensor block clock speed is 36 mhz and is divided down to 1 to 12 mhz for adc operation. interface block command/ status adc temp diodes v in system bus temp sensor/ adc interface to the m8 c ( processor ) core [+] feedback cy7c604xx document number: 001-12395 rev *j page 3 of 33 spi the serial peripheral interconnect (spi) 3-wire protocol uses both edges of the clock to enable synchronous communication without the need for stringent setup and hold requirements. figure 2. basic spi configuration a device can be a master or slav e. a master outputs clock and data to the slave device and inputs slave data. a slave device inputs clock and data from the master device and outputs data for input to the master. together, the master and slave are essen- tially a circular shift register, where the master generates the clocking and initiates data transfers. a basic data transfer occurs when the master sends eight bits of data, along with eight clocks. in any transfer, both master and slave transmit and receive simultaneously. if the master only sends data, the received data from the slave is ignored. if the master wishes to receive data fr om the slave, the master must send dummy bytes to generate the clocking for the slave to send data back. figure 3. spi block diagram spi configuration register (spi_cfg) sets master/slave functionality, clock speed and interrupt select. spi control register (spi_cr) provides four control bits and four status bits for device interfacing and synchronization. the spim hardware has no support for driving the slave select (ss_) signal. the behavior and use of this signal is application and encore v device dependent and, if re quired, must be imple- mented in firmware. there is an additional data input in the spis, slave select (ss_), which is an active low signal. ss_ must be asserted to enable the spis to receive and transmit. ss_ has two high level functions: 1) to allow for the selection of a given slave in a multi-slave environment, and 2) to provide additional clocking for tx data queuing in spi modes 0 and 1. i 2 c slave the i 2 c slave enhanced communications block is a serial-to-parallel processor, designed to interface the encore v lv device to a two-wire i 2 c serial communications bus. to eliminate the need for excessive cpu intervention and overhead, the block provides i 2 c-specific support for status detection and generation of fr aming bits. by default, the i 2 c slave enhanced module is firmware compatible with the previous generation of i 2 c slave functionality. however, this module provides new features that are configurable to implement significant flexibility for both internal and external interfacing. figure 4. i 2 c block diagram mosi miso sclk data is output by both the master and slave on one edge of the clock. data is registered at the input of both devices on the opposite edge of the clock. spi block registers sysclk data_out data_in clk_in clk_out int ss_ sclk mosi, miso sclk mosi, miso configuration[7:0] control[7:0] transmit[7:0] receive[7:0] i2c core i2c basic configuration i2c_cfg i2c_scr i2c_dr plus features hw addr cmp buffer module cpu port buffer ctl 32 byte ram i2c plus slave i2c_addr sda_out scl_in sysclk i2c_en to/from gpio pins standby scl_out sda_in i2c_xstat i2c_xcfg i2c_buf i2c_bp i2c_cp mcu_cp mcu_bp system bus [+] feedback cy7c604xx document number: 001-12395 rev *j page 4 of 33 the basic i 2 c features include: slave, transmitter, and receiver operation. byte processing for low cpu overhead. interrupt or polling cpu interface. support for clock rates of up to 400 khz. 7- or 10-bit addressing (through firmware support). smbus operation (through firmware support). enhanced features of the i 2 c slave enhanced module include: support for 7-bit hardware address compare. flexible data buffering schemes. a "no bus stalling" operating mode. a low power bus monitoring mode. the i 2 c block controls the data (sda ) and the clock (scl) to the external i 2 c interface through direct connections to two dedicated gpio pins. when i 2 c is enabled, these gpio pins are not available for general purpose use. the encore v lv cpu firmware interacts with the block through i/o register reads and writes, and firmware synchronization is implemented through polling and/or interrupts. in the default operating mode, which is firmware compatible with previous versions of i 2 c slave modules, the i 2 c bus is stalled upon every received address or byte, and the cpu is required to read the data or supply data as required before the i 2 c bus continues. however, this i 2 c slave enhanced module provides new data buffering capability as an enhanced feature. in the ezi 2 c buffering mode, the i 2 c slave interface appears as a 32-byte ram buffer to the external i 2 c master. using a simple predefined protocol, the master controls the read and write pointers into the ram. when this method is enabled, the slave never stalls the bus. in this protocol, the data available in the ram (this is managed by the cpu) is valid. additional system resources system resources, some of which have been previously listed, provide additional capability useful to complete systems. additional resources include low voltage detection and power on reset. the following statements describe the merits of each system resource: low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por (power on reset) circuit eliminates t he need for a system supervisor. the 3.6v maximum input, 1.8, 2.5, or 3v selectable output, low dropout regulator (ldo) provides regulation for i/os. a register controlled bypass mode enables the user to disable the ldo. standard cypress psoc ide tools are available for debugging the encore v lv family of parts. getting started the quickest way to understanding the encore v silicon is by reading this data sheet and us ing the psoc designer integrated development environment (ide). th is data sheet is an overview of the encore v integrated circ uit and presents specific pin, register, and electrical specificat ions. for in-depth information, along with detailed programming information, reference the psoc programmable system-on-chip technical reference manual , for cy8c28xxx psoc devices. for up-to-date ordering, packaging, and electrical specification information, reference the latest encore v device data sheets on the web at http://www.cypress.com . development kits development kits are available online from cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training . the training covers a wide variety of topics a nd skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to w ww.cypress.com/cypros . solutions library visit our growing library of solution focused designs at www.cypress.com/solutions . here you can fi nd various appli- cation designs that include firmware and hardware design files that enable you to comple te your designs quickly. technical support for assistance with technical issues, search knowledgebase articles and forums at www.cypress.com/support . if you cannot find an answer to your question, call technical support at 1-800-541-4736. application notes application notes are an excellent introduction to the wide variety of possible psoc designs. they are located here: www.cypress.com/psoc . select application notes under the documentation tab. [+] feedback cy7c604xx document number: 001-12395 rev *j page 5 of 33 development tools psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on-chip (psoc) devices. the psoc designer ide runs on windows xp or windows vista. this system provides design database management by project, an integrated debugger with in -circuit emulator, in-system programming support, and built-i n support for third-party assem- blers and c compilers. psoc designer also supports c language compilers developed specifically for the devices in the encore and psoc families. psoc designer software subsystems chip-level view the chip-level view is a trad itional integrated development environment (ide) based on psoc designer 4.4. choose a base device to work with and then select different onboard analog and digital components called user modules that use the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. configure the user modules for the chosen appli- cation and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy deve lopment of multiple configura- tions and dynamic reconfigurat ion. dynamic reconfiguration enables changing configurations at run time. system-level view the system-level view is a drag-and-drop visual embedded system design environment based on psoc designer. hybrid designs you can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. all views of the project share common code editor, builder, and common deb ug, emulation, and programming tools. code generation tools psoc designer supports multiple third-party c compilers and assemblers. the code generation tools work seamlessly within psoc designer interface and have been tested with a full range of debugging tools. the choice is yours. assemblers. the assemblers allow assembly code to be merged seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers. c language compilers are available that support the encore and psoc families of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all the features of c tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read and program flash, read and write data memory, read and write i/o registers, read and write cpu r egisters, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory lo cations of interest. online help system the online help system displays on line, context-sensitive help for the user. designed for procedural help and quick reference, each functional subsystem has its own context-sensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer in getting started. in-circuit emulator a low cost, high functionality in-circuit emulator (ice) is available for development support. this hardware has the capability to progra m single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with all encore and psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in t he target board and performs full speed (24 mhz) operation. [+] feedback cy7c604xx document number: 001-12395 rev *j page 6 of 33 designing with psoc designer the development process for the encore v device differs from that of a traditional fixed f unction microprocessor. powerful psoc designer tools get the core of your design up and running in minutes instead of hours. the development process can be summarized in the following four steps: 1. select components 2. configure components 3. organize and connect 4. generate, verify, and debug select components the chip-level views provide a library of pre-built, pre-tested hardware peripheral components. these components are called ?user modules.? user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed-signal varieties. configure components each of the components you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. the chip-level user modules are documented in data sheets that are viewed directly in psoc designer. these data sheets explain the internal operation of the component and provide perfor- mance specifications. each data sheet describes the use of each user module parameter and contains other information you may need to successfully implement your design. organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the i/o pins, or connect system-level inputs, outputs, and communication interfaces to each other with valuator functions. in the chip-level view, you perform the selection, configuration, and ro uting so that you have complete control over the use of all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate configuration files? step. this causes psoc designer to generate source code that automat ically configures the device to your specification a nd provides the software for the system. both system-level and chip-lev el designs generate software based on your design. the chip-level design provides application programming interfaces (apis) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. the system-level design also generates a c ma in() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger (access by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabil- ities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. [+] feedback cy7c604xx document number: 001-12395 rev *j page 7 of 33 document conventions acronyms used the following table lists the acronyms that are used in this document. units of measure a units of measure table is locat ed in the electrical specifications section. table 7 on page 16 lists all the abbreviations used to measure the encore v lv devices. numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicat ed by an ?h?, ?b?, or 0x are decimal. acronym description api application programming interface cpu central processing unit gpio general purpose io ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator io input/output lsb least significant bit lvd low voltage detect msb most significant bit por power on reset ppor precision power on reset psoc? programmable system-on-chip? slimo slow imo sram static random access memory [+] feedback cy7c604xx document number: 001-12395 rev *j page 8 of 33 pin configuration 16-pin part pinout figure 5. cy7c60413 16-pin encore v lv device notes 1. during power up or reset event, device p1[0] and p1[1] may dist urb the i2c bus. use alternate pi ns if issues are encountered. 2. these are the in-system serial programming (issp) pins, that are not high z at power on reset (por) p2[5] p1[7] p1[5] p1[3] p0[3] p0[7] vdd p0[4] p1[1] p1[0] p1[2] p2[3] p1[4] xres p0[1] vss qfn/col (top view) 1 2 3 4 12 11 10 9 16 15 14 13 5 6 7 8 table 1. 16-pin part pinout (qfn) pin no. type name description 1 i/o p2[5] digital i/o, crystal out (xout) 2 i/o p2[3] digital i/o, crystal in (xin) 3 iohr p1[7] digital i/o, i 2 c scl, spi ss 4 iohr p1[5] digital i/o, i 2 c sda, spi miso 5 iohr p1[3] digital i/o, spi clk 6 iohr p1[1] (1,2) digital i/o, issp clk, i 2 c scl, spi mosi 7 power vss ground pin 8 iohr p1[0] (1,2) digital i/o, issp data, i 2 c sda, spi clk 9 iohr p1[2] digital i/o 10 iohr p1[4] digital i/o, optional external clock input (extclk) 11 input xres active high external reset with internal pull down 12 iohr p0[4] digital i/o 13 power vdd power pin 14 iohr p0[7] digital i/o 15 iohr p0[3] digital i/o 16 iohr p0[1] digital i/o legend i = input, o = output, oh = 5 ma high output drive, r = regulated output. [+] feedback cy7c604xx document number: 001-12395 rev *j page 9 of 33 32-pin part pinout figure 6. cy7c60445 32-pin encore v lv device p0[1] p2[7] p2[5] p2[3] p2[1] p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3] p0[7] vdd p0[6] p0[4] p0[2] p3[1] p1[7] p0[0] p2[6] p3[0] xres p1[5] p1[3] p1[1] vss p1[0] p1[2] p1[4] p1[6] p2[4] p2[2] p2[0] p3[2] p0[5] table 2. 32-pin part pinout (qfn) pin no. type name description 1 ioh p0[1] digital i/o 2 i/o p2[7] digital i/o 3 i/o p2[5] digital i/o, crystal out (xout) 4 i/o p2[3] digital i/o, crystal in (xin) 5 i/o p2[1] digital i/o 6 i/o p3[3] digital i/o 7 i/o p3[1] digital i/o 8 iohr p1[7] digital i/o, i 2 c scl, spi ss 9 iohr p1[5] digital i/o, i 2 c sda, spi miso 10 iohr p1[3] digital i/o, spi clk 11 iohr p1[1] (1,2) digital i/o, issp clk, i 2 c scl, spi mosi 12 power vss ground connection 13 iohr p1[0] (1,2) digital i/o, issp data, i 2 c sda, spi clk 14 iohr p1[2] digital i/o 15 iohr p1[4] digital i/o, optional external clock input (extclk) 16 iohr p1[6] digital i/o 17 reset input xres active high external reset with internal pull down 18 i/o p3[0] digital i/o 19 i/o p3[2] digital i/o 20 i/o p2[0] digital i/o 21 i/o p2[2] digital i/o 22 i/o p2[4] digital i/o 23 i/o p2[6] digital i/o 24 ioh p0[0] digital i/o 25 ioh p0[2] digital i/o 26 ioh p0[4] digital i/o 27 ioh p0[6] digital i/o [+] feedback cy7c604xx document number: 001-12395 rev *j page 10 of 33 28 power vdd supply voltage 29 ioh p0[7] digital i/o 30 ioh p0[5] digital i/o 31 ioh p0[3] digital i/o 32 power vss ground connection cp power vss center pad must be connected to ground legend i = input, o = output, oh = 5 ma high output drive, r = regulated output. table 2. 32-pin part pinout (qfn) (continued) pin no. type name description [+] feedback cy7c604xx document number: 001-12395 rev *j page 11 of 33 48-pin part pinout figure 7. cy7c60455/cy7c60456 48-pin encore v lv device qfn (top view) p0[1] vss p0[3] p0[5] p0[7] vdd p0[6] 10 11 12 p2[7] p2[5] p2[3] p2[1] p4[3] p4[1] p3[7] p3[5] p3[3] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p0[2] p0[0] p2[6] p2[4] p2[2] p2[0] p3[2] p3[0] xres p1[6] p0[4] 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 nc nc p1[3] p1[1] vss nc nc vdd p1[0] p1[2] p1[4] nc p3[1] p1[7] p1[5] p3[4] p3[6] p4[0] p4[2] nc nc table 3. 48-pin part pinout (qfn) pin no. type name description 1nc nc no connection 2 i/o p2[7] digital i/o 3 i/o p2[5] digital i/o, crystal out (xout) 4 i/o p2[3] digital i/o, crystal in (xin) 5 i/o p2[1] digital i/o 6 i/o p4[3] digital i/o 7 i/o p4[1] digital i/o 8 i/o p3[7] digital i/o 9 i/o p3[5] digital i/o 10 i/o p3[3] digital i/o 11 i/o p3[1] digital i/o 12 iohr p1[7] digital i/o, i 2 c scl, spi ss 13 iohr p1[5] digital i/o, i 2 c sda, spi miso 14 nc nc no connection 15 nc nc no connection 16 iohr p1[3] digital i/o, spi clk 17 iohr p1[1] (1,2) digital i/o, issp clk, i 2 c scl, spi mosi 18 power vss supply ground 19 nc nc no connection 20 nc nc no connection 21 power vdd supply voltage [+] feedback cy7c604xx document number: 001-12395 rev *j page 12 of 33 22 iohr p1[0] (1,2) digital i/o, issp data, i2c sda, spi clk 23 iohr p1[2] digital i/o 24 iohr p1[4] digital i/o, optional external clock input (extclk) 25 iohr p1[6] digital i/o 26 xres ext reset active high external reset with internal pull down 27 i/o p3[0] digital i/o 28 i/o p3[2] digital i/o 29 i/o p3[4] digital i/o 30 i/o p3[6] digital i/o 31 i/o p4[0] digital i/o 32 i/o p4[2] digital i/o 33 i/o p2[0] digital i/o 34 i/o p2[2] digital i/o 35 i/o p2[4] digital i/o 36 i/o p2[6] digital i/o 37 ioh p0[0] digital i/o 38 ioh p0[2] digital i/o 39 ioh p0[4] digital i/o 40 ioh p0[6] digital i/o 41 power vdd supply voltage 42 nc nc no connection 43 nc nc no connection 44 ioh p0[7] digital i/o 45 ioh p0[5] digital i/o 46 ioh p0[3] digital i/o 47 power vss supply ground 48 ioh p0[1] digital i/o cp power vss center pad must be connected to ground legend i = input, o = output, oh = 5 ma high output drive, r = regulated output table 3. 48-pin part pinout (qfn) (continued) pin no. type name description [+] feedback cy7c604xx document number: 001-12395 rev *j page 13 of 33 register reference the section discusses the register s of the encore v lv device. it lists all the registers in mapping tables, in address order. register conventions the register conventions specific to this section are listed in the following table. register mapping tables the encore v lv device has a total register address space of 512 bytes. the register space is also referred to as io space and is broken into two parts: bank 0 (user space) and bank 1 (config- uration space). the xio bit in the flag register (cpu_f) deter- mines which bank the user is currently in. when the xio bit is set, the user is said to be in the ?extended? address space or the ?configuration? registers. table 4. register conventions convention description r read register or bits w write register or bits l logical register or bits c clearable register or bits # access is bit specific [+] feedback cy7c604xx document number: 001-12395 rev *j page 14 of 33 table 5. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 80 c0 prt0ie 01 rw 41 81 c1 02 42 82 c2 03 43 83 c3 prt1dr 04 rw 44 84 c4 prt1ie 05 rw 45 85 c5 06 46 86 c6 07 47 87 c7 prt2dr 08 rw 48 88 i2c_xcfg c8 rw prt2ie 09 rw 49 89 i2c_xstat c9 r 0a 4a 8a i2c_addr ca rw 0b 4b 8b i2c_bp cb r prt3dr 0c rw 4c 8c i2c_cp cc r prt3ie 0d rw 4d 8d cpu_bp cd rw 0e 4e 8e cpu_cp ce r 0f 4f 8f i2c_buf cf rw prt4dr 10 rw 50 90 cur_pp d0 rw prt4ie 11 rw 51 91 stk_pp d1 rw 12 52 92 d2 13 53 93 idx_pp d3 rw 14 54 94 mvr_pp d4 rw 15 55 95 mvw_pp d5 rw 16 56 96 i2c_cfg d6 rw 17 57 97 i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 d9 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c int_clr2 dc rw 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk2 de rw 1f 5f 9f int_msk1 df rw 20 60 a0 int_msk0 e0 rw 21 61 a1 int_sw_en e1 rw 22 62 a2 int_vc e2 rc 23 63 a3 res_wdt e3 w 24 64 a4 int_msk3 e4 rw 25 65 a5 e5 26 66 a6 e6 27 67 a7 e7 28 68 a8 e8 spi_txr 29 w 69 a9 e9 spi_rxr 2a r 6a aa ea spi_cr 2b # 6b ab eb 2c 6c ac ec 2d 6d ad ed 2e 6e ae ee 2f 6f af ef 30 70 pt0_cfg b0 rw f0 31 71 pt0_data1 b1 rw f1 32 72 pt0_data0 b2 rw f2 33 73 pt1_cfg b3 rw f3 34 74 pt1_data1 b4 rw f4 35 75 pt1_data0 b5 rw f5 36 76 pt2_cfg b6 rw f6 37 77 pt2_data1 b7 rw cpu_f f7 rl 38 78 pt2_data0 b8 rw f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # gray fields are reserved and should not be accessed. # access is bit specific. [+] feedback cy7c604xx document number: 001-12395 rev *j page 15 of 33 table 6. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 80 c0 prt0dm1 01 rw 41 81 c1 02 42 82 c2 03 43 83 c3 prt1dm0 04 rw 44 84 c4 prt1dm1 05 rw 45 85 c5 06 46 86 c6 07 47 87 c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 0a 4a 8a ca 0b 4b 8b cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf prt4dm0 10 rw 50 90 d0 prt4dm1 11 rw 51 91 d1 12 52 92 d2 13 53 93 d3 14 54 94 d4 15 55 95 d5 16 56 96 d6 17 57 97 d7 18 58 98 d8 19 59 99 d9 1a 5a 9a da 1b 5b 9b db 1c 5c 9c io_cfg dc rw 1d 5d 9d out_p1 dd rw 1e 5e 9e de 1f 5f 9f df 20 60 a0 osc_cr0 e0 rw 21 61 a1 eco_cfg e1 # 22 62 a2 osc_cr2 e2 rw 23 63 a3 vlt_cr e3 rw 24 64 a4 vlt_cmp e4 r 25 65 a5 e5 26 66 a6 e6 27 67 a7 e7 28 68 a8 imo_tr e8 w spi_cfg 29 rw 69 a9 ilo_tr e9 w 2a 6a aa ea 2b 6b ab slp_cfg eb rw 2c tmp_dr0 6c rw ac slp_cfg2 ec rw 2d tmp_dr1 6d rw ad slp_cfg3 ed rw 2e tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 70 b0 f0 31 71 b1 f1 32 72 b2 f2 33 73 b3 f3 34 74 b4 f4 35 75 b5 f5 36 76 b6 f6 37 77 b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be fe 3f 7f bf ff gray fields are reserved and should not be accessed. # access is bit specific. [+] feedback cy7c604xx document number: 001-12395 rev *j page 16 of 33 electrical specifications this section presents the dc and ac electric al specifications of the encore v lv dev ices. for the most up to date electrical specifications, verify that you have the most recent data sheet available by visiting the company web site at http://www.cypress.com. figure 8. voltage versus cpu frequency figure 9. imo frequency trim options the following table lists the units of me asure that are used in this chapter. 3.6v 5.7 mhz 24 mhz cpu frequency vdd voltage 1.71v v a l i d o p e r a t i n g re g i o n 3.6v 750 khz 6 mhz 24 mhz imo frequency vdd voltage 3 mhz 1.71v slimo mode = 01 12 mhz slimo mode = 00 slimo mode = 10 table 7. units of measure symbol unit of measure symbol unit of measure o c degree celsius w microwatts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nanoampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k kilohm ohm mhz megahertz pa picoampere m megaohm pf picofarad a microampere pp peak-to-peak f microfarad ppm parts per million h microhenry ps picosecond s microsecond sps samples per second v microvolts sigma: one standard deviation vrms microvolts root-mean-square v volts [+] feedback cy7c604xx document number: 001-12395 rev *j page 17 of 33 absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature table 8. absolute maximum ratings symbol description conditions min typ max units t stg storage temperature [3] higher storage temperatures reduces data retention time. recommended storage temperature is +25c 25c. extended duration storage temperatures above 85 o c degrades reliability. ?55 +25 +125 c vdd supply voltage relative to vss ?0.5 ? +6.0 v v io dc input voltage vss ? 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tristate vss ?0.5 ? vdd + 0.5 v i mio maximum current into any port pin ?25 ? +50 ma esd electro static discharge voltage human body model esd 2000 ? ? v lu latch up current in accordance with jesd78 standard ? ? 200 ma notes 3. higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures above 85 o c degrade reliability. 4. the temperature rise from ambient to junction is package specific. see thermal impedances on page 30 . the user must limit the power consumption to comply with this requirement. table 9. operating temperature symbol description conditions min typ max units t ac ambient commercial temperature 0 +70 c t jc operational commercial die temperature [4] the temperature rise from ambient to junction is package specific. refer the table ?thermal impedances? on page 30. the user must limit the power consumption to comply with this requirement. 0 +85 c [+] feedback cy7c604xx document number: 001-12395 rev *j page 18 of 33 dc electrical characteristics dc chip level specifications ta b l e 1 0 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. table 10. dc chip level specifications symbol description conditions min typ max units vdd [5] supply voltage see table titled dc por and lvd specifications on page 22. 1.71 ? 3.6 v i dd24 supply current, imo = 24 mhz conditions are vdd 3.0v, t a = 25 o c, cpu = 24 mhz no i2c/spi ? 2.9 4.0 ma i dd12 supply current, imo = 12 mhz conditions are vdd 3.0v, t a = 25 o c, cpu = 12 mhz no i2c/spi ? 1.7 2.6 ma i dd6 supply current, imo = 6 mhz conditions are vdd 3.0v, t a = 25 o c, cpu = 6 mhz no i2c/spi ? 1.2 1.8 ma i sb1 standby current with por, lvd, and sleep timer vdd 3.0v, t a = 25 o c, i/o regulator turned off ? 1.1 1.5 a i sb0 deep sleep current vdd 3.0v, t a = 25 o c, i/o regulator turned off ? 0.1 ? a note 5. when vdd remains in the range from 1.71v to 1.9v for more than 50 sec, the slew rate when moving from the 1.71v to 1.9v rang e to greater than 2v must be slower than 1v/500 usec to avoid triggeri ng por. the only other restriction on slew rates for any other voltage range or transi tion is the sr power_up parameter. [+] feedback cy7c604xx document number: 001-12395 rev *j page 19 of 33 dc general purpose i/o specifications the following tables list guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 1. 71v to 3.6v a nd 0 c t a 70 c. typical parameters apply to 3.3v at 25 c. these are for design guidance only. table 11. 3.0v to 3.6v dc gpio specifications symbol description conditions min typ max units r pu pull up resistor 4 5.6 8 k v oh1 high output voltage port 2 or 3 pins ioh < 10 a, maximum of 10 ma source current in all i/os vdd - 0.2 ? ? v v oh2 high output voltage port 2 or 3 pins ioh = 1 ma, maximum of 20 ma source current in all i/os vdd - 0.9 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh < 10 a, maximum of 10 ma source current in all i/os vdd - 0.2 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 5 ma, maximum of 20 ma source current in all i/os vdd - 0.9 ? ? v v oh5 high output voltage port 1 pins with ldo regulator enabled for 3v out ioh < 10 a, vdd > 3.1v, maximum of 4 i/os all sourcing 5 ma 2.85 3.00 3.3 v v oh6 high output voltage port 1 pins with ldo regulator enabled for 3v out ioh = 5 ma, vdd > 3.1v, maximum of 20 ma source current in all i/os 2.20 ? ? v v oh7 high output voltage port 1 pins with ldo enabled for 2.5v out ioh < 10 a, vdd > 2.7v, maximum of 20 ma source current in all i/os 2.35 2.50 2.75 v v oh8 high output voltage port 1 pins with ldo enabled for 2.5v out ioh = 2 ma, vdd > 2.7v, maximum of 20 ma source current in all i/os 1.90 ? ? v v oh9 high output voltage port 1 pins with ldo enabled for 1.8v out ioh < 10 a, vdd > 2.7v, maximum of 20 ma source current in all i/os 1.60 1.80 2.1 v v oh10 high output voltage port 1 pins with ldo enabled for 1.8v out ioh = 1 ma, vdd > 2.7v, maximum of 20 ma source current in all i/os 1.20 ? ? v v ol low output voltage iol = 25 ma, vdd > 3.3v, maximum of 60 ma sink current on even port pins (for example, p0[2] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[5]) ??0.75v v il input low voltage ? ? 0.80 v v ih input high voltage 2.00 ? v v h input hysteresis voltage ? 80 ? mv i il input leakage (absolute value) ? 0.001 1 a c pin pin capacitance package and pin dependent te m p = 2 5 o c 0.5 1.7 5 pf [+] feedback cy7c604xx document number: 001-12395 rev *j page 20 of 33 table 12. 2.4v to 3.0v dc gpio specifications symbol description conditions min typ max units r pu pull up resistor 45.68k v oh1 high output voltage port 2 or 3 pins ioh < 10 a, maximum of 10 ma source current in all i/os vdd - 0.2 ? ? v v oh2 high output voltage port 2 or 3 pins ioh = 0.2 ma, maximum of 10 ma source current in all i/os vdd - 0.4 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh < 10 a, maximum of 10 ma source current in all i/os vdd - 0.2 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 2 ma, maximum of 10 ma source current in all i/os vdd - 0.5 ? ? v v oh5a high output voltage port 1 pins with ldo enabled for 1.8v out ioh < 10 a, vdd > 2.4v, maximum of 20 ma source current in all i/os. 1.50 1.80 2.10 v v oh6a high output voltage port 1 pins with ldo enabled for 1.8v out ioh = 1 ma, vdd > 2.4v, maximum of 20 ma source current in all i/os 1.20 ? ? v v ol low output voltage iol = 10 ma, maximum of 30 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.75 v v il input low voltage ? ? 0.72 v v ih input high voltage 1.4 ? v v h input hysteresis voltage ? 80 ? mv i il input leakage (absolute value) ? 0.001 1 a c pin capacitive load on pins package and pin dependent te m p = 2 5 o c 0.5 1.7 5 pf table 13. 1.71v to 2.4v dc gpio specifications symbol description conditions min typ max units r pu pull up resistor 45.68k v oh1 high output voltage port 2 or 3 pins ioh = 10 a, maximum of 10 ma source current in all i/os vdd - 0.2 ? ? v v oh2 high output voltage port 2 or 3 pins ioh = 0.5 ma, maximum of 10 ma source current in all i/os vdd - 0.5 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 100 a, maximum of 10 ma source current in all i/os vdd - 0.2 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 2 ma, maximum of 10 ma source current in all i/os vdd - 0.5 ? ? v v ol low output voltage iol = 5 ma, maximum of 20 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ??0.4v v il input low voltage ? ? 0.3 x vdd v v ih input high voltage 0.65 x vdd ? v v h input hysteresis voltage ? 80 ? mv i il input leakage (absolute value) ? 0.001 1 a c pin capacitive load on pins package and pin dependent. te m p = 2 5 o c 0.5 1.7 5 pf [+] feedback cy7c604xx document number: 001-12395 rev *j page 21 of 33 adc electrical specifications table 14. adc user module electrical specifications symbol description conditions min typ max units input v in input voltage range 0 vrefadc v c iin input capacitance 5 pf r in input resistance equiva lent switched cap input resistance for 8-, 9-, or 10-bit resolution 1/(500ff* data clock) 1/(400ff* data clock) 1/(300ff* data clock) reference v refadc adc reference voltage 1.14 1.26 v conversion rate f clk data clock source is chip?s internal main oscillator. see ac chip-level specifications for accuracy 2.25 6 mhz s8 8-bit sample rate da ta clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) 23.4375 ksps s10 10-bit sample rate data clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) 5.859 ksps dc accuracy res resolution can be set to 8-, 9-, or 10-bit 8 10 bits dnl differential nonlinearity -1 +2 lsb inl integral nonlinearity -2 +2 lsb e offset offset error 8-bit resolution 0 3.2 19.2 lsb 10-bit resolution 0 12.8 76.8 lsb e gain gain error for any resolution -5 +5 %fsr power i adc operating curr ent 2.1 2.6 ma psrr power supply rejection ratio psrr (vdd>3.0v) 24 db psrr (vdd<3.0v) 30 db [+] feedback cy7c604xx document number: 001-12395 rev *j page 22 of 33 dc por and lvd specifications ta b l e 1 5 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. dc programming specifications ta b l e 1 6 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. table 15. dc por and lvd specifications symbol description min typ max units v ppor0 v ppor1 v ppor2 v ppor3 vdd value for ppor trip (6) porlev[1:0] = 00b, hpor = 0 porlev[1:0] = 00b, hpor = 1 porlev[1:0] = 01b, hpor = 1 porlev[1:0] = 10b, hpor = 1 1.61 1.66 2.36 2.60 2.82 1.71 2.41 2.66 2.95 v v v v v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 vdd value for lvd trip vm[2:0] = 000b (7) vm[2:0] = 001b (8) vm[2:0] = 010b (9) vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b (10) 2.40 2.64 2.85 2.95 3.06 1.84 1.75 2.45 2.71 2.92 3.02 3.13 1.9 1.8 2.51 2.78 2.99 3.09 3.20 2.32 1.84 v v v v v v v table 16. dc programming specifications symbol description min typ max units vdd iwrite supply voltage for flash write operations 1.71 ? 5.25 v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? v il [11] v v ihp input high voltage during programming or verify 0.65xvdd iwrite ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify (11) ? ? 0.2 ma i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify (11) ? ? 1.5 ma v olp output low voltage during programming or verify ? ? vss + 0.75 v v ohp output high voltage during programming or verify vdd iwrite - 0.9v ? vdd iwrite v flash enpb flash write endurance (13) 50,000 ? ? cycles flash dr flash data retention (14) 10 20 ? years notes 6. vdd must be greater than or equal to 1.71v during startup, reset from the xres pin, or reset from watchdog. 7. always greater than 50 mv above v ppor1 for falling supply. 8. always greater than 50 mv above v ppor2 for falling supply. 9. always greater than 50 mv above v ppor3 for falling supply. 10. always greater than 50 mv above v ppor0 voltage for falling supply. 11. driving internal pull down resistor. 12. see appropriate dc general purpose i/o specifications table. 13. erase/write cycles per block. 14. following maximum flash write cycles at tamb = 55c and tj = 70c. [+] feedback cy7c604xx document number: 001-12395 rev *j page 23 of 33 ac electrical characteristics ac chip level specifications ta b l e 1 7 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. table 17. ac chip level specifications symbol description conditions min typ max units f cpu processing frequency 5.7 ? 25.2 mhz f 32k1 internal low speed oscillator frequency trimmed for 3.3 v operation using factory trim values 19 32 50 khz f 32k_u internal low speed oscillator (ilo) untrimmed frequency) 13 32 82 khz f 32k2 internal low speed oscillator frequency untrimmed 13 32 82 khz f imo24 internal main oscillator stability for 24 mhz 5% 22.8 24 25.2 mhz f imo12 internal main oscillator stability for 12 mhz 11.4 12 12.6 mhz f imo6 internal main oscillator stability for 6 mhz 5.7 6.0 6.3 mhz dc imo duty cycle of imo 40 50 60 % dc ilo internal low speed oscillator duty cycle 40 50 60 % sr power_up power supply slew rate ? ? 250 v/ms t xrst external reset pulse width at power up after supply voltage is valid 1 ms t xrst2 external reset pulse width after power up [15] applies after part has booted 10 s note 15. the minimum required xres pulse length is longer when programming the device (see table 20 on page 25 ). [+] feedback cy7c604xx document number: 001-12395 rev *j page 24 of 33 ac general purpose io specifications ta b l e 1 8 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. figure 10. gpio timing diagram table 18. ac gpio specifications symbol description conditions min typ max units f gpio gpio operating frequency normal strong mode, port 0, 1 0 0 ? ? 6 mhz for 1.71v cy7c604xx document number: 001-12395 rev *j page 27 of 33 table 22. spi master ac specifications symbol description conditions min typ max units f sclk sclk clock frequency v dd 2.4v v dd < 2.4v 6 3 mhz dc sclk duty cycle 50 % t setup miso to sclk setup time v dd 2.4v v dd < 2.4v 60 100 ns t hold sclk to miso hold time 40 ns t out_val sclk to mosi valid time 40 ns t out_high mosi high time 40 ns table 23.spi slave ac specifications symbol description conditions min typ max units f sclk sclk clock frequency v dd 2.4v v dd < 2.4v 12 6 mhz t low sclk low time 41.67 ns t high sclk high time 41.67 ns t setup mosi to sclk setup time 30 ns t hold sclk to mosi hold time 50 ns t ss_miso ss high to miso valid 153 ns t sclk_miso sclk to miso valid 125 ns t ss_high ss high time 50 ns t ss_clk time from ss low to first sclk 2/sclk ns t clk_ss time from last sclk to ss high 2/sclk ns [+] feedback cy7c604xx document number: 001-12395 rev *j page 28 of 33 package diagram this section illustrates the packaging spec ifications for the encore v lv device, al ong with the thermal impedances for each pa ckage. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the encore v lv emulation tools and their dimensions, refer to the development kit. packaging dimensions figure 13. 16-pin (3 x 3 mm) qfn (001-09116) 001-09116 *d [+] feedback cy7c604xx document number: 001-12395 rev *j page 29 of 33 figure 14. 32-pin (5 x 5 x 0.55 mm) qfn (001-42168) figure 15. 48-pin qfn (7 x 7x 0.90 mm) sawn (001-13191) 001-42168 *c 001-13191 *d [+] feedback cy7c604xx document number: 001-12395 rev *j page 30 of 33 package handling some ic packages require baking before they are soldered onto a pcb to remove moisture that may have been absorbed after leavin g the factory. a label on the package has details about the actual bake temperature and the minimum bake time to remove this mois ture. the maximum bake time is the aggregate time that the parts exposed to the bake temper ature. exceeding this exposure may degrade device reliability. thermal impedances capacitance on crystal pins solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 24.package handling parameter description minimum typical maximum unit t baketemp bake temperature 125 see package label o c t baketime bake time see package label 72 hours package typical ja (17) 16 qfn 32.69 o c/w 32 qfn (18) 19.51 o c/w 48 qfn (18) 17.68 o c/w table 25. typical package capacitance on crystal pins package package capacitance 32 qfn 3.2 pf 48 qfn 3.3 pf package minimum peak temperature (19) maximum peak temperature 16 qfn 240 o c 260 o c 32 qfn 240 o c 260 o c 48 qfn 240 o c 260 o c [+] feedback cy7c604xx document number: 001-12395 rev *j page 31 of 33 ordering information ordering code package information flash sram no. of gpios target applications cy7c60413-16lkxc 16-pin qfn (3x3 mm) 8k 1k 13 feature-rich wireless mouse CY7C64013-16LKXCT 16-pin qfn - (tape and reel) (3x3 mm) 8k 1k 13 feature-rich wireless mouse cy7c60445-32lqxc 32-pin qfn (5x5x0.55 mm) 16k 1k 28 feature-rich wireless mouse cy7c60445-32lqxct 32-pin qfn - (tape and reel) (5x5x0.55 mm) 16k 1k 28 feature-rich wireless mouse cy7c60455-48ltxc 48-pin qfn (7x7x0.9 mm) 16k 1k 36 mid-tier wireless keyboard cy7c60455-48ltxct 48-pin qfn - (tape and reel) (7x7x0.9 mm) 16k 1k 36 mid-tier wireless keyboard cy7c60456-48ltxc 48-pin qfn (7x7x0.9 mm) 32k 2k 36 feature-rich wireless keyboard cy7c60456-48ltxct 48-pin qfn - (tape and reel) (7x7x0.9 mm) 32k 2k 36 feature-rich wireless keyboard notes 17. t j = t a + power x ja. 18. to achieve the thermal impedance specified for the package, solder the center thermal pad to the pcb ground plane. 19. higher temperatures may be required based on the solder melti ng point. typical temperatures for solder are 220 5c with sn -pb or 245 5c with sn-ag-cu paste. refer to the solder manufacturer specifications. [+] feedback cy7c604xx document number: 001-12395 rev *j page 32 of 33 document history page document title: cy7c604xx, encore? v low voltage microcontroller document number: 001-12395 rev. ecn no. orig. of change submission date description of change ** 626516 tyj see ecn new data sheet *a 735721 tyj/ari see ecn added new block diagram, replaced tbds, corrected values, updated pinout infor- mation, changed part number to reflect new specifications. *b 1120504 ari see ecn corrected the description to pin 29 on table 1, the typ/max values for i sb0 on the dc chip-level specifications, and the min voltage value for vdd iwrite in the dc programming specifications table. corrected flash write endurance minimum value in the dc programming speci- fications table. corrected the flash erase time max value and the flash block write time max value in the ac programming specifications table. implemented new latest template. *c 1225864 aesa/ari see ecn corrected the description to pin 13, 29 on table 1 and 22,44 on table 2. added sections register reference, regi ster conventions and register mapping tables. corrected max values on the dc chip-level specifications table. *d 1446763 aesa see ecn changed t eraseb parameter, max value to 18ms in table 13, ac programming specification. *e 1639963 aesa see ecn post to www.cypress.com *f 2138889 tyj/pyrs see ecn updated ordering code table: - ordering code changed for 32-qfn package: from -32lkxc to -32ltxc - added a new package type ? ?ltxc? for 48-qfn - included tape and reel ordering code for 32-qfn and 48-qfn packages changed active current values at 24, 12 and 6mhz in table ?dc chip-level speci- fications? - idd24: 2.15 to 3.1ma - idd12: 1.45 to 2.0ma - idd6: 1.1 to 1.5ma added information on using p1[0] and p1[1] as the i2c interface during por or reset events *g 2583853 tyj/pyrs/ hmt 10/10/08 converted from preliminary to final adc resolution changed from 10-bit to 8-bit on page1, spi master and slave ? speeds changed rephrased battery monitoring clause in page 1 to include ?with external compo- nents? included adc specifications table voh5, voh7, voh9 specs changed flash data retention ? condition added to note [15] input leakage spec changed to 25 na max under ac char, frequency accuracy of ilo corrected gpio rise time for ports 0,1 and ports 2,3 made common ac programming specifications updated included ac programmi ng cycle timing diagram ac spi specification updated spec change for 32-qfn package input leakage current maximum value changed to 1 ua maximum specification for v oh5a parameter changed from 2.0 to 2.1v minimum voltages for f spim and f spis specifications changed from 1.8v to 1.71v (table 18) updated v ohv parameter in table 13 updated thermal impedance values for the packages - table 20. update development tools, add designing with psoc designer. edit, fix links and table format. update tms. update maximum data in table 12. dc por and lvd specifications. [+] feedback document number: 001-12395 rev *j revised september 15, 2009 page 33 of 33 encore?, psoc designer? and programmable system-on-chip? are trademarks and psoc? is a registered trademark of cypress semicond uctor corporation. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i2c components from cypress or one of its sublicensed associated companies conveys a license under the philips i2c patent rights to use these components in an i2c system , provided that the system confor ms to the i2c standard speci fication as defined by philips. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c604xx ? cypress semiconductor corporation, 2006-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com *h 2653717 dvja/pyrs 02/04/09 changed master pa ge from cy7c60445, cy7c6045x to cy7c604xx. updated features, functional overview, de velopment tools, and designing with psoc designer sections. removed ?gui - graphical user interfac e? from document conventions acronym table. added figure 1 and table 1 (16-pin part in formation) to pin configurations section. removed ?o - only a read/write register or bits? in table 4 edited table 8: removed 10-bit resolution information and corrected units column. added figure 9 (16-pin part information) to package dimensions section. added ?package handling? section. added 8k part ?cy7c60413-16lkxc? to ordering information. *i 2714694 dvja/aesa 06/04/2009 updated block diagram. added 10-bit adc, spi, and i2c slave sections. adc resolution changed from 8-bit to 10-bit updated figure 9: 5.7 mhz minimum cpu freqency updated table 15 ac chip level specs figure 8: changed minimum cpu frequency from 750 khz to 5.7 mhz *j 2764460 dvja/aesa 09/15/2009 ad ded footnote #5 to table 10: dc chip level specs added f 32k2 (untrimmed) spec to table 17: ac chip level specs changed t ramp spec to sr power_up in table 17: ac chip level specs changed table 14: adc specs added table 25: typical package capacitance on crystal pins document title: cy7c604xx, encore? v low voltage microcontroller document number: 001-12395 [+] feedback |
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